10 technologies to look forward to in 2010

From EETimes
10 technologies to look forward to in 2010
Posted: 23 Nov 2009


EE Times has compiled emerging technologies will be worth watching out for in 2010.
Recessions are the times of change when R&D investments get pushed to the fore. It is well known that when markets and prosperity return they never return in exactly the same form that they went away.

We have deliberately favored the hardware- and physically-based side of the technology landscape, although software is also likely to increase its impact and importance in 2010.

There are also some technology trends that are so self-evident and long-term that we have not listed them. We would include amongst these the need to reduce power consumption and the need to pursue low-carbon and reduced materials content solutions. We see these as drivers for some of the more detailed technologies we list below. We don't claim to have a perfectly accurate piezoelectric crystal ball, but some technologies and some technology providers are going to change the landscape in 2010. The ten technologies listed below, in no particular order, might just be part of our changing times.

1. Biofeedback/thought-control of electronics
A number of companies and research institutions have shown how brain waves, captured using sensors on a skull cap or headset, can be used to control computer systems. The applications are medical—giving communications and control of the environment to heavily disabled people—military and, increasingly, in consumer and computer games control interfaces. This may seem like science fiction but the thought-control human-computer interface is here now and is being promoted by companies such as Emotiv Systems Inc.

2. Printed electronics
The possibility of the rapid printing of multiple conductive, insulating and semiconductive layers to form electronic circuits holds out the prospect of much lower cost ICs than those prepared by conventional fabrication methods. Printing semiconductors usually implies the use of organic materials (although see below) with very different performance to silicon. It is also implies much larger minimum geometries than can be attained in silicon. But there are applications that can benefit from modest performance on flexible subtrates at low cost; the RFID tag is one and the active-matrix backplane for displays is another.

Kovio Inc., a privately-held pioneer in printed silicon electronics, has been plowing the printed electronics furrow since the company was founded in 2001, and in July 2009 announced that it had raised $20 million in Series E financing. Kovio said it planned to use the money to commence volume shipments of its Kovio RF barcodes.

3. Plastic memory
This is allied to printed electronics as it may well be produced using printing, it may well have modest performance compared to silicon, but it is expected to be low cost. One pioneer in this area is Thin Film Electronics ASA, which has tried for a number of years to get the technology out the door and spent some time working with Intel.

The technology is based on polythiophenes, a family of polymers that display ferroelectric properties. The memories are rewritable, non-volatile, show more than ten years data retention and one million cycles, according to Thin Film Electronics. In September 2009 PolyIC GmbH & Co. KG used the technology to make a 20-bit memory on a roll-to-roll line using polyethylene terephthalate (PET) as the substrate.

4. Maskless lithography
For many people the main question that hangs over semiconductor lithography is when will extreme UV lithography take over from immersion lithography? But there is a dark horse in the race, maskless lithography based on an electron beam, which is being pioneered by Mapper Lithography BV.

In July 2009 Mapper shipped a 300mm electron-beam lithography platform to CEA-Leti in Grenoble, France, where it was set to be used for R&D by Taiwan Semiconductor Manufacturing Co. Ltd. TSMC is one of the key researchers of lithography and the company's interest in the Mapper technology is at the very least keeping the likes of ASML and Nikon working hard.

5. Parallel processing
This technology is already here in the form of the dual- and quad-core PC processors and the multicore heterogeneous processors used for embedded applications. However, there is as yet little formal understanding of how multiple processors will be programmed and used for the utmost computational and power efficiency.

This is one of the core problems in Information Technology that has faced the industry since the advent of the processor and we are still working away at it. Initiatives such as OpenCL and Cuda speak to that as do the prospect of using graphics processors as general purpose processors, as well as FPGAs and software programmable processor arrays. We expect a lot more activity in 2010.

6. Energy harvesting
Energy harvesting is not a new idea. We have had the motion-powered wristwatch for many years. But as electronic circuits move from consuming milliwatts to consuming microwatts an interesting thing happens. It becomes possible to contemplate drawing power for those circuits, not from the electricity grid or from a battery but from a variety of ambient phenomena. And this is expected to have far-reaching impact.

One of the early applications is to have vibration-powered, wireless sensors in place on machinery, in vehicles. The battery-less aspect of such sensors removes the need for maintenance. EnOcean GmbH has pioneered the use of wireless, batteryless switches for use in building automation and is now helping to drive the EnOcean Alliance to form standards.

Nokia is looking at energy harvesting in the context of the mobile phone but has stressed it has no prototype as yet. But in 2010 all makers of mobile equipment have to be looking at energy harvesting to, at least, augment the battery life of their equipment.

7. Bio-electronics and wetware
This might be a bit more on the research side than the development side for 2010, but the coming together of the biological and the electronic is ripe for exploitation. We are used to the inclusion of hardware within animals in the form of under-the-skin tags for animals and heart pacemakers for human beings and the need to improve and reduce the cost of medical care is being felt acutely.

As the industry's capabilities in MEMS and organic electronics fabrication improves the scope for integration of tissues and electronic circuitry increases. Lab-on-a-chip is one manifestation of the technology, and here is an example from IBM disclosed recently, but it is also possible to grow biological cells on electronically addressable substrates. The opportunities for in-vitro diagnostics are clear. Information about the electrical behavior of individual cells and their reactions to drugs is a major focus for research in cardiac and neural ailments such as Alzheimer's or Parkinson's disease.

So, in short, we expect a lot of research and the continued emergence of bio-electronics as a mainstream activity.

8. Resistive RAM/memristor
The pursuit of the universal memory goes on. It needs to be simple like a DRAM, or preferably even simpler as those capacitors are a problem to scaling. It needs to be able to retain data for years with the power off and able to be used millions of times. It needs to be simple to make using conventional methods and with materials that are not out of place in conventional wafer fabs. And we still haven't found it yet.

Or have we?

In 2009 Unity Semiconductor Corp. emerged from seven years of stealthy research with its conductive metal oxide (CMOx) technology, although we are pleased to note that EE Times was reporting on Unity in April 2006. But 2009 has also seen the arrival on our radar screens of 4DS Inc., Qs Semiconductor Corp. and Adesto Technologies Inc.

We are also aware that many of the larger IDMs are active in RRAM. And the reference to the memristor is because two-terminal devices that display a memory-effect in their resistance characteristic are effectively the practical implementation of the theoretical work, championed by Hewlett-Packard Labs, on the memristor, often described as the fourth passive circuit element after resistors, capacitors and inductors.

9. Through-silicon via
The depth of the interconnect stack on top of the leading-edge silicon surface is deep and can vary markedly in minimum geometry. We have speculated that this could result in a splitting of front-end fab production into surface and local interconnect followed by higher stack connection, possibly in different wafer fabs.

The desire, for marketing as well as technical reasons, to mount multiple die in single packages is also driving a need for more sophisticated interconnect and the arrival of the through-silicon-via passing completely through a silicon wafer or die is clearly important in creating 3D packages.

In May 2009 austriamicrosystems started producing TSV parts on a foundry basis, targeting suppliers of devices for 3-D integration of CMOS ICs and sensor components. Expect more of the same in 2010.

10. Battery technologies
We have become so used to Moore's law and the steady miniaturization of microelectronics it is easy to become frustrated with a technology that does not double in performance every two years. But battery technology is relatively mature and is not driven by the same forces as the integrated circuit. Indeed if energy storage becomes too dense it can become dangerous.

Nonetheless we all rely increasingly on batteries for energy storage and to power our various gadgets. Indeed it is arguable that without further breakthroughs in battery technology for electric vehicles the compatibility of the automobile and sustainable green transportation is in jeopardy. So the pressure is on.

Recent spins on nickel- and lithium-based battery chemistries, such as nickel oxyhydroxide, olivine-type lithium iron phosphate and nanowires, are gunning to displace the venerable but problematic alkaline-manganese dioxide formulations. ReVolt Technology, a developer of rechargeable zinc-air batteries, has selected Portland, Oregon as the location for its U.S. headquarters and manufacturing center. We expect similar developments to come on apace in 2010, and every smart battery is set to provide a power management IC opportunity.

- Peter Clarke
EE Times

maximum sideband setting in spectrerf psp and pnoise analysis

What number should be set for maximum sideband for psp or pnoise analysis?

All the noise computations in PSP involve noise folding effects. The
maxsideband parameter specifies the maximum sideband included
for summing noise contributions either up-converted or downconverted
to the output at the interested frequency. The contribution
of the noise source to the output is modulated by the periodic
transfer function. Modulation with a periodic transfer function is
convolution with the discrete spectrum of the transfer function.
Maxsideband specifies the number of sidebands to be involved in
this calculation.

Reference: http://w2.cadence.com/whitepapers/pspapn1.pdf
http://w2.cadence.com/whitepapers/pspapn1.pdf

So it depends on the beat frequency in your setting and the interested sidebands of the circuits. A resonable number is required.

In one go I cleared all the LVS errors

I am working on the test chip layout. As the design is finishing, I seem to have enough time before the deadline. When it is under control, I am a bit relaxed and getting more patience.

After running lvs, i have some errors which I used to be scared of as it is quite time consuming to find out those errors. But today, I am very smoothly to clear all errors in one go at a short time. Below is a few notes in solving the LVS errors:

(1) For incorrect nets, if two layout nets point to one source net, most probably the two layout nets are short somewhere;
(2) Layout nets showing missing, the matching source net is also showing missing, they might not be connected;
(3) if sub-block is LVS clear, but top-block's LVS error point to the sub-block, most probably the connection is wrong at the top-level.

Difference between spectre, spectreS, Hspice, HspiceS

there are two simulation "methodes" in cadence dfII:
1. direct simulation approach, spectre, HspiceD,
2. socket simulation approach, spectreS, HspiceS

the direct simulation approach is more efficient than the socket simulations, because there the netlist have to be translated first into a cds-spice netlist.

spectreS stands for spectre in Spice-Socket. So the netlist is similar to spice. In the analog artist the components are netlisted as Spice primitives where most simulator commands are in spectre native language. Spectre themselve differentiate between spectre native syntax and Spice syntax with a language switch command.

The socket comes from old cadence spice called cdsSpice.
All the third party simulators can be integrated to cadence using this cdsSpice socket(example hspiceS, eldo etc smartSpice mica tispice).

Cadence Artist <=> cdsSpice <=> Thirdparty simulators

However, this is kind of obsolete now.
Cadence now promotes Direct Simulation Interface(OASIS) for third party vendors. So no more socketing. For example,
The hspiceS will become hspiceD but the simulator is still the same.
Bottomline it is all about the netlisting but the simulator is just the same.

Quated from http://www.edaboard.com/ftopic74615.html

ZigBee Alliance Members Awarded Nearly $500 Million From U.S. Smart Grid Grants

ZigBee Alliance Members Awarded Nearly $500 Million From U.S. Smart Grid Grants
November 2, 2009

San Ramon, CA -- The ZigBee® Alliance, a global ecosystem of companies creating wireless solutions for use in energy management, commercial and consumer applications, congratulates its members who were selected to receive funding for their Smart Grid efforts as part of the United States American Reinvestment and Recovery Act. ZigBee Alliance members received a total of $478,823,415, representing a total investment of more than $1.2 billion in smart grid programs with ZigBee Smart Energy as the standard for home area networks.

Individual ZigBee members received between $4 million and $200 million dollars for their Smart Grid projects. Members earning grants include: CenterPoint Energy, Baltimore Gas and Electric, Reliant Energy Retail Services, San Diego Gas and Electric, Honeywell International and Whirlpool. Grants were awarded for a variety of ZigBee Smart Energy products and services, including large smart meter programs covering 4.7 million meters, installation of a variety of devices such as programmable communicating thermostats, in-home displays and load controllers, plus expediting the development of smart appliances.

ZigBee Smart Energy enables wireless communication between utility companies and everyday household devices such as smart thermostats and appliances. It is the underlying technology providing consumers with dynamic pricing information as well as programming control over smart appliances. This control allows consumers to manage their power use and how much they spend on energy while participating in demand response programs designed to help utilities manage generation needs during peak power periods.

"ZigBee Alliance members have been taking an active role in developing the Smart Grid for years and these grants are recognition for our members' leadership on this important initiative," said Bob Heile, chairman of the ZigBee Alliance. "With ZigBee Smart Energy's position in the marketplace and its role as an initial interoperable standard by NIST for the critical home area network piece of the Smart Grid, we expect that those utilities and product manufacturers sitting on the sidelines will adopt ZigBee."

ZigBee Smart Energy – The Standard for Energy Management and Efficiency
ZigBee Smart Energy enables wireless communication between utility companies and common household devices such as smart thermostats and appliances. It improves energy efficiency by allowing consumers to choose interoperable products from different manufacturers giving them the means to manage their energy consumption more precisely using automation and near real-time information. It also helps utility companies implement new advanced metering and demand response programs to drive greater energy management and efficiency, while responding to changing government requirements.

ZigBee: Control your world
ZigBee is the global wireless language connecting dramatically different devices to work together and enhance everyday life. The ZigBee Alliance is a non-profit association of more than 300 member companies driving development of ZigBee wireless technology. The Alliance promotes world-wide adoption of ZigBee as the leading wirelessly networked, sensing and control standard for use in energy, home, commercial and industrial areas. For more information, visit: www.ZigBee.org.

SOURCE: The ZigBee Alliance

Paper about current-driven passive mixers from the Oct. Issue of JSSC 2009

Looking through the Oct. issue of the IEEE JSSC 2009, I am only interested in the paper "Analysis and Optimization of Current-Driven Passive Mixers in Narrowband Direct-Conversion Receivers".

I lost my patience before figuring out so many mathematical analysis, and skipped all equations and summarized the main points as below:

1. It mentions that the flicker
noise of the switches appears at the mixer output proportional to
the DC current, and refers to some techniques proposed
to lower the flicker noise corner in the active mixers.

2. The paper compares two widely used current buffer structures,
which are the common-gate and the opamp with RC
feedback.it will be shown that the opamp-based design is advantageous for better performance in terms of eliminating the IQ cross-talk as well as different
high- and low-side gains.

3.

4. The op-amp design is also interesting in common mode feed back control.The input and output share the same common mode voltage.

Return loss

One professor commented that return loss is usually specified in receiver input, for example LNA. Is is a specification in power amplifier?

Goolged the answer, it is a general definition. Actually it can be used for any device in power transmission. In power amplifier, input return loss and output return loss are also used in specification, but some people prefer to use VSWR instead of input/output return loss.

 

Home > Library > Miscellaneous > Wikipedia

In telecommunications, Return loss or Reflection loss is the reflection of signal power resulting from the insertion of a device in a transmission line or optical fiber. It is usually expressed as a ratio in dB relative to the transmitted signal power.
If the power supplied by the source is P_I (incident power) and the power reflected is P_R, then the return loss in dB is given by

Optical Return Loss is a positive number, historically ORL has also been referred to as a negative number. Within the industry expect to see ORL referred to variably as a positive or negative number.
This ORL sign ambiguity can lead to confusion when referring to a circuit as having high or low return loss; so remember:- High Return Loss = lower reflected power = large ORL number = generally good. Low Return Loss = higher reflected power = small ORL number = generally bad.

Electrical

In metallic conductor systems, reflections of a signal traveling down a conductor can occur at a discontinuity or impedance mismatch. The ratio of the amplitude of the reflected wave V_r to the amplitude of the incident wave V_i is known as the reflection coefficient Γ.

When the source and load impedances are known values, the reflection coefficient is given by

where Z_S is the impedance toward the source and Z_L is the impedance toward the load.
Return loss is simply the magnitude of the reflection coefficient in dB. Since power is proportional to the square of the voltage, then return loss is given by

where the vertical bars indicate magnitude. Thus, a large positive return loss indicates the reflected power is small relative to the incident power, which indicates good impedance match from source to load.
When the actual transmitted (incident) power and the reflected power are known (i.e. through measurements and/or calculations), then the return loss in dB can be calculated as the difference between the incident power P_i (in dBm) and the reflected power P_r (in dBm).

RL(dB) = P_i(dBm) − P_r(dBm)

How to change the cursor to cross in cadence virtuoso layout

Using the Display Options Form
The Display Options form controls the appearance of objects and the behavior of commands in this cellview.


Nets shows flight lines between objects on the same net. If your design contains many nets, your screen may turn white, causing the instTerms on top of the instance to not be seen. To see the instTerms, turn on Instance Pins and the flight lines will not display, allowing the instTerms to be seen.

Access Edges shows routing edges of pins.

Instance Pins shows pins in instances.

Array Icons shows outlines of array cells when Display Levels suppresses cell details.

Label Origins marks the origins of labels with diamond markers.

Dynamic Hilight marks the edge, object, or point that would be selected if a point selection were made. When Dynamic Hilight is on and your cellview contains a large number of objects, cursor motion may slow down. You can increase the cursor motion speed by turning this off.

Net Expressions displays the net expression instead of the terminal name of a pin. When there are net expressions in instances, the terminal name is displayed, not the net expression, even when Net Expressions is set on.

Stretch Handles displays the handles on a Relative Object Design parameterized cell (pcell) that indicate that the pcell can be stretched. A stretch handle is a named set of coordinates assigned to a specific parameter of the pcell. Stretch handles look like small diamonds. For information about stretchable pcells, see "Stretchable Parameterized Cells" in the Virtuoso Relative Object Design User Guide.



Axes displays the cellview X and Y axes.

Path Borders shows the border edges of paths. Turn it off to display only path centerlines.

Instance Origins marks cell instance origins with diamonds when you set Display Levels to show only instance outlines.

EIP Surround (edit-in-place) displays the surrounding design when you edit a cell in place.

Pin Names shows terminal names of pins that have pin name text displays.

Dot Pins displays the centers of dot pins with diamond markers.

Use True BBox when on, displays the instance master bounding box. When off, displays the cellview bounding box, which can cause large designs to open faster because masters are opened down to the display stop level only.

Cross Cursor displays the cursor as dot shaped or as dotted-line cross shaped.

Via Shapes displays via attributes. When Via Shapes is set to off (the default), vias are displayed as the bounding box of each via. When set to on via attributes are graphically displayed, resulting in detailed images. For large designs, setting via shapes to on will increase the amount of time it takes to render a design.

Show Name Of, when Display Levels is set to show only instance outlines, sets whether the instance name (for example, I1) or the master cell name appears on each instance.

Array Display

Full displays all instances in the array.


Border displays only the instances around the outside edge of the array.


Source displays only the instance at the origin of the array.


Display Levels sets the first (From) and last (To) levels in the design hierarchy that can be seen in detail. The hierarchy levels are numbered 0 to 32. The top cellview is level 0, instances inside of it are level 1, and so forth.

Type controls the grid display.

none turns off the grid display.


dots displays a dot for each grid point.


lines makes a grid of lines, like a graph.


Minor Spacing and Major Spacing set the number of user units between the visible grid. Minor grid points are white, major grid points are green by default.

X Snap Spacing and Y Snap Spacing set the distance at which the cursor can snap between grid points along the X axis and the Y axis. This is your drawing grid.

Filter determines how much detail of a design is displayed in the cellview. The filter can affect how fast the screen redraws. A smaller filter size allows more objects to display, which can cause the screen to redraw more slowly. A larger filter size allows fewer objects to display, which can cause the screen to redraw faster and can be useful when redrawing large, dense designs.

Size controls the size of the objects that are filtered out. With a smaller filter, more of the design displays. When Size is set to 3, the default, objects smaller than 3 pixels are filtered; objects larger than 3 pixels are not filtered.


Style controls how the filtered objects are displayed. Filtered objects appear either filled with their layer color, outlined with their layer color, or empty and nothing is displayed.


Snap Modes locks your cursor to the grid while drawing or editing.

Create controls how line segments snap to the grid as you create objects.


Edit controls how line segments of objects snap to the grid as you move or copy them and how edges or corners move as you stretch them.


Cellview specifies that you want to store, load, or delete the display settings to or from the cellview.

Library specifies that you want to store, load, or delete the display settings to or from the library of the edit cellview.

Tech Library specifies that you want to store, load, or delete the display settings to or from the technology library of the edit cellview.

File specifies the file to which you want to store or from which you want to load the settings.

Save To saves the current settings to either the cellview, library of the cellview, technology library of the cellview, or a specified file. If you are saving to a file, the settings from both the Layout Editor Options and Display Options forms are saved.

Load From sets the current settings to either the cellview, library of the cellview, the technology library of the cellview, or a specified file. If you saved to a file, the settings for both the Layout Editor Options and Display Options forms are loaded.

Delete From deletes the display settings that were saved to either the cellview, library of the cellview, or technology library of the cellview.

(from : http://jas.eng.buffalo.edu/courses/ee549/cadence/virtuosoDoc/chap4.html)

Check quota

Recently my account quota is almost full, I have to do house cleaning while doing simulation. This command is useful for me to find out large size file/folder.

du -sh ; will summarize the folder's size
du -sh *, will summarize each file/subfolder 's size

Introduction

As an analog and RF IC design engineer, I would like to create this blog to share and discuss the analog and RF circuit design techniques.

It has been a number of times that I could not get the right information which I did come across some time ago. I hope this blog will help me blog down those information in a properly organized way, which may be useful for me or others some day.