In one go I cleared all the LVS errors

I am working on the test chip layout. As the design is finishing, I seem to have enough time before the deadline. When it is under control, I am a bit relaxed and getting more patience.

After running lvs, i have some errors which I used to be scared of as it is quite time consuming to find out those errors. But today, I am very smoothly to clear all errors in one go at a short time. Below is a few notes in solving the LVS errors:

(1) For incorrect nets, if two layout nets point to one source net, most probably the two layout nets are short somewhere;
(2) Layout nets showing missing, the matching source net is also showing missing, they might not be connected;
(3) if sub-block is LVS clear, but top-block's LVS error point to the sub-block, most probably the connection is wrong at the top-level.